255 lines
6.5 KiB
C
255 lines
6.5 KiB
C
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/*
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* Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_CPUFEATURE_H
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#define __ASM_CPUFEATURE_H
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#include <asm/cpucaps.h>
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#include <asm/hwcap.h>
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#include <asm/sysreg.h>
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/*
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* In the arm64 world (as in the ARM world), elf_hwcap is used both internally
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* in the kernel and for user space to keep track of which optional features
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* are supported by the current system. So let's map feature 'x' to HWCAP_x.
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* Note that HWCAP_x constants are bit fields so we need to take the log.
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*/
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#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
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#define cpu_feature(x) ilog2(HWCAP_ ## x)
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#ifndef __ASSEMBLY__
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#include <linux/bug.h>
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#include <linux/jump_label.h>
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#include <linux/kernel.h>
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/* CPU feature register tracking */
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enum ftr_type {
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FTR_EXACT, /* Use a predefined safe value */
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FTR_LOWER_SAFE, /* Smaller value is safe */
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FTR_HIGHER_SAFE,/* Bigger value is safe */
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};
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#define FTR_STRICT true /* SANITY check strict matching required */
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#define FTR_NONSTRICT false /* SANITY check ignored */
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#define FTR_SIGNED true /* Value should be treated as signed */
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#define FTR_UNSIGNED false /* Value should be treated as unsigned */
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struct arm64_ftr_bits {
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bool sign; /* Value is signed ? */
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bool strict; /* CPU Sanity check: strict matching required ? */
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enum ftr_type type;
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u8 shift;
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u8 width;
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s64 safe_val; /* safe value for FTR_EXACT features */
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};
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/*
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* @arm64_ftr_reg - Feature register
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* @strict_mask Bits which should match across all CPUs for sanity.
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* @sys_val Safe value across the CPUs (system view)
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*/
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struct arm64_ftr_reg {
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const char *name;
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u64 strict_mask;
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u64 sys_val;
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const struct arm64_ftr_bits *ftr_bits;
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};
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extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
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/* scope of capability check */
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enum {
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SCOPE_SYSTEM,
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SCOPE_LOCAL_CPU,
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};
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struct arm64_cpu_capabilities {
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const char *desc;
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u16 capability;
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int def_scope; /* default scope */
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bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
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int (*enable)(void *); /* Called on all active CPUs */
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union {
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struct { /* To be used for erratum handling only */
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u32 midr_model;
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u32 midr_range_min, midr_range_max;
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};
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struct { /* Feature register checking */
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u32 sys_reg;
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u8 field_pos;
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u8 min_field_value;
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u8 hwcap_type;
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bool sign;
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unsigned long hwcap;
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};
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};
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};
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extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
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extern struct static_key_false arm64_const_caps_ready;
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bool this_cpu_has_cap(unsigned int cap);
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static inline bool cpu_have_feature(unsigned int num)
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{
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return elf_hwcap & (1UL << num);
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}
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/* System capability check for constant caps */
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static inline bool __cpus_have_const_cap(int num)
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{
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if (num >= ARM64_NCAPS)
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return false;
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return static_branch_unlikely(&cpu_hwcap_keys[num]);
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}
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static inline bool cpus_have_cap(unsigned int num)
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{
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if (num >= ARM64_NCAPS)
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return false;
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return test_bit(num, cpu_hwcaps);
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}
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static inline bool cpus_have_const_cap(int num)
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{
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if (static_branch_likely(&arm64_const_caps_ready))
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return __cpus_have_const_cap(num);
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else
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return cpus_have_cap(num);
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}
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static inline void cpus_set_cap(unsigned int num)
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{
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if (num >= ARM64_NCAPS) {
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pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
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num, ARM64_NCAPS);
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} else {
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__set_bit(num, cpu_hwcaps);
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}
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}
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static inline int __attribute_const__
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cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
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{
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return (s64)(features << (64 - width - field)) >> (64 - width);
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}
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static inline int __attribute_const__
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cpuid_feature_extract_signed_field(u64 features, int field)
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{
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return cpuid_feature_extract_signed_field_width(features, field, 4);
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}
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static inline unsigned int __attribute_const__
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cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
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{
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return (u64)(features << (64 - width - field)) >> (64 - width);
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}
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static inline unsigned int __attribute_const__
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cpuid_feature_extract_unsigned_field(u64 features, int field)
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{
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return cpuid_feature_extract_unsigned_field_width(features, field, 4);
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}
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static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
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{
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return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
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}
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static inline int __attribute_const__
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cpuid_feature_extract_field(u64 features, int field, bool sign)
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{
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return (sign) ?
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cpuid_feature_extract_signed_field(features, field) :
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cpuid_feature_extract_unsigned_field(features, field);
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}
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static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
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{
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return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);
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}
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static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
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{
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return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
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cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
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}
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static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
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{
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u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
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return val == ID_AA64PFR0_EL0_32BIT_64BIT;
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}
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void __init setup_cpu_features(void);
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void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
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const char *info);
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void enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps);
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void check_local_cpu_capabilities(void);
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void update_cpu_errata_workarounds(void);
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void __init enable_errata_workarounds(void);
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void verify_local_cpu_errata_workarounds(void);
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u64 read_system_reg(u32 id);
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static inline bool cpu_supports_mixed_endian_el0(void)
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{
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return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
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}
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static inline bool system_supports_32bit_el0(void)
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{
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return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
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}
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static inline bool system_supports_mixed_endian_el0(void)
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{
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return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
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}
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static inline bool system_uses_ttbr0_pan(void)
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{
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return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
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!cpus_have_cap(ARM64_HAS_PAN);
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}
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#define ARM64_SSBD_UNKNOWN -1
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#define ARM64_SSBD_FORCE_DISABLE 0
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#define ARM64_SSBD_KERNEL 1
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#define ARM64_SSBD_FORCE_ENABLE 2
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#define ARM64_SSBD_MITIGATED 3
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static inline int arm64_get_ssbd_state(void)
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{
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#ifdef CONFIG_ARM64_SSBD
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extern int ssbd_state;
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return ssbd_state;
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#else
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return ARM64_SSBD_UNKNOWN;
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#endif
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}
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#ifdef CONFIG_ARM64_SSBD
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void arm64_set_ssbd_mitigation(bool state);
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#else
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static inline void arm64_set_ssbd_mitigation(bool state) {}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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