259 lines
6.6 KiB
C
259 lines
6.6 KiB
C
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/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*****************************************************************************
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*
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* Filename:
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* ---------
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* bq24297.h
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*
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* Project:
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* --------
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* Android
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*
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* Description:
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* ------------
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* bq24297 header file
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*
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* Author:
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* -------
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*
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****************************************************************************/
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#ifndef _bq24297_SW_H_
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#define _bq24297_SW_H_
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#define bq24297_CON0 0x00
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#define bq24297_CON1 0x01
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#define bq24297_CON2 0x02
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#define bq24297_CON3 0x03
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#define bq24297_CON4 0x04
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#define bq24297_CON5 0x05
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#define bq24297_CON6 0x06
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#define bq24297_CON7 0x07
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#define bq24297_CON8 0x08
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#define bq24297_CON9 0x09
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#define bq24297_CON10 0x0A
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/**********************************************************
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*
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* [MASK/SHIFT]
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*
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*********************************************************/
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/* CON0 */
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#define CON0_EN_HIZ_MASK 0x01
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#define CON0_EN_HIZ_SHIFT 7
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#define CON0_VINDPM_MASK 0x0F
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#define CON0_VINDPM_SHIFT 3
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#define CON0_IINLIM_MASK 0x07
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#define CON0_IINLIM_SHIFT 0
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/* CON1 */
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#define CON1_REG_RST_MASK 0x01
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#define CON1_REG_RST_SHIFT 7
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#define CON1_WDT_RST_MASK 0x01
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#define CON1_WDT_RST_SHIFT 6
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#define CON1_OTG_CONFIG_MASK 0x01
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#define CON1_OTG_CONFIG_SHIFT 5
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#define CON1_CHG_CONFIG_MASK 0x01
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#define CON1_CHG_CONFIG_SHIFT 4
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#define CON1_SYS_MIN_MASK 0x07
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#define CON1_SYS_MIN_SHIFT 1
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#define CON1_BOOST_LIM_MASK 0x01
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#define CON1_BOOST_LIM_SHIFT 0
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/* CON2 */
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#define CON2_ICHG_MASK 0x3F
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#define CON2_ICHG_SHIFT 2
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#define CON2_FORCE_20PCT_MASK 0x1
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#define CON2_FORCE_20PCT_SHIFT 0
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/* CON3 */
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#define CON3_IPRECHG_MASK 0x0F
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#define CON3_IPRECHG_SHIFT 4
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#define CON3_ITERM_MASK 0x0F
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#define CON3_ITERM_SHIFT 0
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/* CON4 */
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#define CON4_VREG_MASK 0x3F
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#define CON4_VREG_SHIFT 2
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#define CON4_BATLOWV_MASK 0x01
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#define CON4_BATLOWV_SHIFT 1
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#define CON4_VRECHG_MASK 0x01
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#define CON4_VRECHG_SHIFT 0
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/* CON5 */
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#define CON5_EN_TERM_MASK 0x01
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#define CON5_EN_TERM_SHIFT 7
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#define CON5_TERM_STAT_MASK 0x01
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#define CON5_TERM_STAT_SHIFT 6
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#define CON5_WATCHDOG_MASK 0x03
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#define CON5_WATCHDOG_SHIFT 4
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#define CON5_EN_TIMER_MASK 0x01
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#define CON5_EN_TIMER_SHIFT 3
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#define CON5_CHG_TIMER_MASK 0x03
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#define CON5_CHG_TIMER_SHIFT 1
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/* CON6 */
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#define CON6_TREG_MASK 0x03
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#define CON6_TREG_SHIFT 0
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/* CON7 */
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#define CON7_DPDM_EN_MASK 0x01
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#define CON7_DPDM_EN_SHIFT 7
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#define CON7_TMR2X_EN_MASK 0x01
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#define CON7_TMR2X_EN_SHIFT 6
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#define CON7_BATFET_Disable_MASK 0x01
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#define CON7_BATFET_Disable_SHIFT 5
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#define CON7_INT_MASK_MASK 0x03
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#define CON7_INT_MASK_SHIFT 0
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/* CON8 */
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#define CON8_VBUS_STAT_MASK 0x03
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#define CON8_VBUS_STAT_SHIFT 6
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#define CON8_CHRG_STAT_MASK 0x03
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#define CON8_CHRG_STAT_SHIFT 4
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#define CON8_DPM_STAT_MASK 0x01
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#define CON8_DPM_STAT_SHIFT 3
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#define CON8_PG_STAT_MASK 0x01
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#define CON8_PG_STAT_SHIFT 2
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#define CON8_THERM_STAT_MASK 0x01
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#define CON8_THERM_STAT_SHIFT 1
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#define CON8_VSYS_STAT_MASK 0x01
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#define CON8_VSYS_STAT_SHIFT 0
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/* CON9 */
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#define CON9_WATCHDOG_FAULT_MASK 0x01
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#define CON9_WATCHDOG_FAULT_SHIFT 7
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#define CON9_OTG_FAULT_MASK 0x01
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#define CON9_OTG_FAULT_SHIFT 6
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#define CON9_CHRG_FAULT_MASK 0x03
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#define CON9_CHRG_FAULT_SHIFT 4
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#define CON9_CHRG_INPUT_FAULT_MASK 0x01
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#define CON9_CHRG_THERMAL_SHUTDOWN_FAULT_MASK 0x02
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#define CON9_CHRG_TIMER_EXPIRATION_FAULT_MASK 0x03
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#define CON9_BAT_FAULT_MASK 0x01
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#define CON9_BAT_FAULT_SHIFT 3
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#define CON9_NTC_FAULT_MASK 0x03
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#define CON9_NTC_FAULT_SHIFT 0
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#define CON9_NTC_COLD_FAULT_MASK 0x02
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#define CON9_NTC_HOT_FAULT_MASK 0x01
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/* CON10 */
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#define CON10_PN_MASK 0x07
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#define CON10_PN_SHIFT 5
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#define CON10_Rev_MASK 0x07
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#define CON10_Rev_SHIFT 0
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/* REG09 status */
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enum BQ_FAULT {
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BQ_NORMAL_FAULT = 0,
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BQ_WATCHDOG_FAULT,
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BQ_OTG_FAULT,
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BQ_CHRG_NORMAL_FAULT,
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BQ_CHRG_INPUT_FAULT,
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BQ_CHRG_THERMAL_FAULT,
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BQ_CHRG_TIMER_EXPIRATION_FAULT,
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BQ_BAT_FAULT,
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BQ_NTC_COLD_FAULT,
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BQ_NTC_HOT_FAULT,
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BQ_FAULT_MAX
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};
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/**********************************************************
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*
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* [Extern Function]
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*
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*********************************************************/
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/* CON0---------------------------------------------------- */
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extern void bq24297_set_en_hiz(u32 val);
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extern void bq24297_set_vindpm(u32 val);
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extern void bq24297_set_iinlim(u32 val);
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extern u32 bq24297_get_iinlim(void);
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/* CON1---------------------------------------------------- */
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extern void bq24297_set_reg_rst(u32 val);
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extern void bq24297_set_wdt_rst(u32 val);
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extern void bq24297_set_otg_config(u32 val);
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extern void bq24297_set_chg_config(u32 val);
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extern void bq24297_set_sys_min(u32 val);
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extern void bq24297_set_boost_lim(u32 val);
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/* CON2---------------------------------------------------- */
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extern void bq24297_set_ichg(u32 val);
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extern void bq24297_set_force_20pct(u32 val);
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/* CON3---------------------------------------------------- */
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extern void bq24297_set_iprechg(u32 val);
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extern void bq24297_set_iterm(u32 val);
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/* CON4---------------------------------------------------- */
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extern void bq24297_set_vreg(u32 val);
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extern void bq24297_set_batlowv(u32 val);
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extern void bq24297_set_vrechg(u32 val);
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/* CON5---------------------------------------------------- */
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extern void bq24297_set_en_term(u32 val);
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extern void bq24297_set_term_stat(u32 val);
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extern void bq24297_set_watchdog(u32 val);
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extern void bq24297_set_en_timer(u32 val);
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extern void bq24297_set_chg_timer(u32 val);
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/* CON6---------------------------------------------------- */
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extern void bq24297_set_treg(u32 val);
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/* CON7---------------------------------------------------- */
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extern u32 bq24297_get_dpdm_status(void);
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extern void bq24297_set_dpdm_en(u32 val);
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extern void bq24297_set_tmr2x_en(u32 val);
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extern void bq24297_set_batfet_disable(u32 val);
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extern void bq24297_set_int_mask(u32 val);
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/* CON8---------------------------------------------------- */
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extern u32 bq24297_get_system_status(void);
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extern u32 bq24297_get_vbus_stat(void);
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extern u32 bq24297_get_chrg_stat(void);
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extern u32 bq24297_get_pg_stat(void);
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extern u32 bq24297_get_vsys_stat(void);
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/* --------------------------------------------------------- */
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extern void bq24297_dump_register(void);
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extern u32 bq24297_read_interface(u8 RegNum, u8 *val, u8 MASK, u8 SHIFT);
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s32 bq24297_control_interface(int cmd, void *data);
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extern int hw_charger_type_detection(void);
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/* spm utility */
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extern int slp_get_wake_reason(void);
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#endif /* _bq24297_SW_H_ */
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