47 lines
1.7 KiB
Text
47 lines
1.7 KiB
Text
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Renesas Bus State Controller (BSC)
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==================================
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The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
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Bridge", or "External Bus Interface") can be found in several Renesas ARM SoCs.
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It provides an external bus for connecting multiple external devices to the
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SoC, driving several chip select lines, for e.g. NOR FLASH, Ethernet and USB.
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While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
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domain, and may have a gateable functional clock.
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Before a device connected to the BSC can be accessed, the PM domain
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containing the BSC must be powered on, and the functional clock
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driving the BSC must be enabled.
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The bindings for the BSC extend the bindings for "simple-pm-bus".
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Required properties
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- compatible: Must contain an SoC-specific value, and "renesas,bsc" and
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"simple-pm-bus" as fallbacks.
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SoC-specific values can be:
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"renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
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"renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
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- #address-cells, #size-cells, ranges: Must describe the mapping between
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parent address and child address spaces.
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- reg: Must contain the base address and length to access the bus controller.
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Optional properties:
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- interrupts: Must contain a reference to the BSC interrupt, if available.
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- clocks: Must contain a reference to the functional clock, if available.
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- power-domains: Must contain a reference to the PM domain, if available.
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Example:
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bsc: bus@fec10000 {
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compatible = "renesas,bsc-sh73a0", "renesas,bsc",
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"simple-pm-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x20000000>;
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reg = <0xfec10000 0x400>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&zb_clk>;
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power-domains = <&pd_a4s>;
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};
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