143 lines
4.1 KiB
C
143 lines
4.1 KiB
C
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _CORESIGHT_TMC_H
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#define _CORESIGHT_TMC_H
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#include <linux/miscdevice.h>
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#define TMC_RSZ 0x004
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#define TMC_STS 0x00c
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#define TMC_RRD 0x010
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#define TMC_RRP 0x014
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#define TMC_RWP 0x018
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#define TMC_TRG 0x01c
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#define TMC_CTL 0x020
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#define TMC_RWD 0x024
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#define TMC_MODE 0x028
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#define TMC_LBUFLEVEL 0x02c
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#define TMC_CBUFLEVEL 0x030
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#define TMC_BUFWM 0x034
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#define TMC_RRPHI 0x038
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#define TMC_RWPHI 0x03c
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#define TMC_AXICTL 0x110
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#define TMC_DBALO 0x118
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#define TMC_DBAHI 0x11c
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#define TMC_FFSR 0x300
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#define TMC_FFCR 0x304
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#define TMC_PSCR 0x308
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#define TMC_ITMISCOP0 0xee0
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#define TMC_ITTRFLIN 0xee8
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#define TMC_ITATBDATA0 0xeec
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#define TMC_ITATBCTR2 0xef0
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#define TMC_ITATBCTR1 0xef4
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#define TMC_ITATBCTR0 0xef8
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/* register description */
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/* TMC_CTL - 0x020 */
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#define TMC_CTL_CAPT_EN BIT(0)
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/* TMC_STS - 0x00C */
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#define TMC_STS_TMCREADY_BIT 2
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#define TMC_STS_FULL BIT(0)
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#define TMC_STS_TRIGGERED BIT(1)
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/* TMC_AXICTL - 0x110 */
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#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
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#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
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#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
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#define TMC_AXICTL_WR_BURST_16 0xF00
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/* TMC_FFCR - 0x304 */
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#define TMC_FFCR_FLUSHMAN_BIT 6
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#define TMC_FFCR_EN_FMT BIT(0)
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#define TMC_FFCR_EN_TI BIT(1)
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#define TMC_FFCR_FON_FLIN BIT(4)
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#define TMC_FFCR_FON_TRIG_EVT BIT(5)
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#define TMC_FFCR_TRIGON_TRIGIN BIT(8)
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#define TMC_FFCR_STOP_ON_FLUSH BIT(12)
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enum tmc_config_type {
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TMC_CONFIG_TYPE_ETB,
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TMC_CONFIG_TYPE_ETR,
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TMC_CONFIG_TYPE_ETF,
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};
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enum tmc_mode {
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TMC_MODE_CIRCULAR_BUFFER,
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TMC_MODE_SOFTWARE_FIFO,
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TMC_MODE_HARDWARE_FIFO,
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};
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enum tmc_mem_intf_width {
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TMC_MEM_INTF_WIDTH_32BITS = 1,
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TMC_MEM_INTF_WIDTH_64BITS = 2,
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TMC_MEM_INTF_WIDTH_128BITS = 4,
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TMC_MEM_INTF_WIDTH_256BITS = 8,
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};
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/**
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* struct tmc_drvdata - specifics associated to an TMC component
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* @base: memory mapped base address for this component.
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* @dev: the device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
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* @spinlock: only one at a time pls.
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* @buf: area of memory where trace data get sent.
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* @paddr: DMA start location in RAM.
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* @vaddr: virtual representation of @paddr.
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* @size: trace buffer size.
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* @len: size of the available trace.
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* @mode: how this TMC is being used.
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* @config_type: TMC variant, must be of type @tmc_config_type.
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* @memwidth: width of the memory interface databus, in bytes.
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* @trigger_cntr: amount of words to store after a trigger.
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*/
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struct tmc_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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struct miscdevice miscdev;
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spinlock_t spinlock;
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bool reading;
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char *buf;
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dma_addr_t paddr;
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void __iomem *vaddr;
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u32 size;
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u32 len;
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u32 mode;
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enum tmc_config_type config_type;
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enum tmc_mem_intf_width memwidth;
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u32 trigger_cntr;
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};
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/* Generic functions */
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void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
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void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
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void tmc_enable_hw(struct tmc_drvdata *drvdata);
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void tmc_disable_hw(struct tmc_drvdata *drvdata);
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/* ETB/ETF functions */
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int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
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int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata);
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extern const struct coresight_ops tmc_etb_cs_ops;
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extern const struct coresight_ops tmc_etf_cs_ops;
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/* ETR functions */
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int tmc_read_prepare_etr(struct tmc_drvdata *drvdata);
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int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata);
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extern const struct coresight_ops tmc_etr_cs_ops;
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#endif
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