316 lines
8 KiB
C
316 lines
8 KiB
C
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/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*****************************************************************************
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*
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* Filename:
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* ---------
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* bq25890.h
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*
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* Project:
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* --------
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* Android
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*
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* Description:
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* ------------
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* bq25890 header file
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*
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* Author:
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* -------
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*
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****************************************************************************/
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#ifndef _bq25890_SW_H_
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#define _bq25890_SW_H_
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#define bq25890_CON0 0x00
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#define bq25890_CON1 0x01
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#define bq25890_CON2 0x02
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#define bq25890_CON3 0x03
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#define bq25890_CON4 0x04
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#define bq25890_CON5 0x05
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#define bq25890_CON6 0x06
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#define bq25890_CON7 0x07
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#define bq25890_CON8 0x08
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#define bq25890_CON9 0x09
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#define bq25890_CON10 0x0A
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#define bq25890_CON11 0x0B
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#define bq25890_CON12 0x0C
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#define bq25890_CON13 0x0D
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#define bq25890_CON14 0x0E
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#define bq25890_CON15 0x0F
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#define bq25890_CON16 0x10
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#define bq25890_CON17 0x11
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#define bq25890_CON18 0x12
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#define bq25890_CON19 0x13
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#define bq25890_CON20 0x14
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/**********************************************************
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*
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* [MASK/SHIFT]
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*
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*********************************************************/
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/* CON0 */
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#define CON0_EN_HIZ_MASK 0x01
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#define CON0_EN_HIZ_SHIFT 7
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#define CON0_IINLIM_MASK 0x3F
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#define CON0_IINLIM_SHIFT 0
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/* CON1 */
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#define CON1_VINDPM_OS_MASK 0x1F
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#define CON1_VINDPM_OS_SHIFT 0
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/* CON2 */
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#define CON2_ICO_EN_MASK 0x01
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#define CON2_ICO_EN_SHIFT 4
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#define CON2_HVDCP_EN_MASK 0x01
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#define CON2_HVDCP_EN_SHIFT 3
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#define CON2_MAXC_EN_MASK 0x01
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#define CON2_MAXC_EN_SHIFT 2
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#define CON2_FORCE_DPDM_MASK 0x01
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#define CON2_FORCE_DPDM_SHIFT 1
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#define CON2_AUTO_DPDM_MASK 0x01
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#define CON2_AUTO_DPDM_SHIFT 0
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/* CON3 */
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#define CON3_WDT_RST_MASK 0x01
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#define CON3_WDT_RST_SHIFT 6
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#define CON3_OTG_CONFIG_MASK 0x01
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#define CON3_OTG_CONFIG_SHIFT 5
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#define CON3_CHG_CONFIG_MASK 0x01
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#define CON3_CHG_CONFIG_SHIFT 4
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#define CON3_SYS_MIN_MASK 0x07
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#define CON3_SYS_MIN_SHIFT 1
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/* CON4 */
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#define CON4_EN_PUMPX_MASK 0x01
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#define CON4_EN_PUMPX_SHIFT 7
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#define CON4_ICHG_MASK 0x7F
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#define CON4_ICHG_SHIFT 0
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/* CON5 */
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#define CON5_IPRECHG_MASK 0x0F
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#define CON5_IPRECHG_SHIFT 4
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#define CON5_ITERM_MASK 0x0F
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#define CON5_ITERM_SHIFT 0
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/* CON6 */
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#define CON6_VREG_MASK 0x3F
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#define CON6_VREG_SHIFT 2
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#define CON6_BATLOWV_MASK 0x01
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#define CON6_BATLOWV_SHIFT 1
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#define CON6_VRECHG_MASK 0x01
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#define CON6_VRECHG_SHIFT 0
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/* CON7 */
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#define CON7_EN_TERM_MASK 0x01
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#define CON7_EN_TERM_SHIFT 7
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#define CON7_WATCHDOG_MASK 0x03
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#define CON7_WATCHDOG_SHIFT 4
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#define CON7_EN_TIMER_MASK 0x01
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#define CON7_EN_TIMER_SHIFT 3
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#define CON7_CHG_TIMER_MASK 0x03
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#define CON7_CHG_TIMER_SHIFT 1
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/* CON8 */
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#define CON8_BAT_COMP_MASK 0x7
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#define CON8_BAT_COMP_SHIFT 5
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#define CON8_VCLAMP_MASK 0x7
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#define CON8_VCLAMP_SHIFT 2
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#define CON8_TREG_MASK 0x03
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#define CON8_TREG_SHIFT 0
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/* CON9 */
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#define CON9_BATFET_DIS_MASK 0x01
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#define CON9_BATFET_DIS_SHIFT 5
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#define CON9_JEITA_VSET_MASK 0x01
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#define CON9_JEITA_VSET_SHIFT 4
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#define CON9_PUMPX_UP_MASK 0x01
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#define CON9_PUMPX_UP_SHIFT 1
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#define CON9_PUMPX_DN_MASK 0x01
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#define CON9_PUMPX_DN_SHIFT 0
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/* CON10 */
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#define CON10_BOOST_LIM_MASK 0x07
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#define CON10_BOOST_LIM_SHIFT 0
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#define CON10_BOOSTV_MASK 0x0F
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#define CON10_BOOSTV_SHIFT 4
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/* CON11 */
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#define CON11_VBUS_STAT_MASK 0x07
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#define CON11_VBUS_STAT_SHIFT 5
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#define CON11_CHRG_STAT_MASK 0x03
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#define CON11_CHRG_STAT_SHIFT 3
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#define CON11_PG_STAT_MASK 0x01
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#define CON11_PG_STAT_SHIFT 2
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#define CON11_SDP_STAT_MASK 0x01
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#define CON11_SDP_STAT_SHIFT 1
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#define CON11_VSYS_STAT_MASK 0x01
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#define CON11_VSYS_STAT_SHIFT 0
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/* CON12 */
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#define CON12_WATCHDOG_FAULT_MASK 0x01
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#define CON12_WATCHDOG_FAULT_SHIFT 7
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#define CON12_OTG_FAULT_MASK 0x01
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#define CON12_OTG_FAULT_SHIFT 6
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#define CON12_CHRG_FAULT_MASK 0x03
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#define CON12_CHRG_FAULT_SHIFT 4
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#define CON12_CHRG_INPUT_FAULT_MASK 0x01
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#define CON12_CHRG_THERMAL_SHUTDOWN_FAULT_MASK 0x02
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#define CON12_CHRG_TIMER_EXPIRATION_FAULT_MASK 0x03
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#define CON12_BAT_FAULT_MASK 0x01
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#define CON12_BAT_FAULT_SHIFT 3
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#define CON12_NTC_FAULT_MASK 0x07
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#define CON12_NTC_FAULT_SHIFT 0
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/* CON13 */
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#define CON13_FORCE_VINDPM_MASK 0x01
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#define CON13_FORCE_VINDPM_SHIFT 7
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#define CON13_VINDPM_MASK 0x7F
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#define CON13_VINDPM_SHIFT 0
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/* CON19 */
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#define CON19_VDPM_STAT_MASK 0x01
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#define CON19_VDPM_STAT_SHIFT 7
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#define CON19_IDPM_STAT_MASK 0x01
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#define CON19_IDPM_STAT_SHIFT 6
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#define CON19_IDPM_LIM_MASK 0x3F
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#define CON19_IDPM_LIM_SHIFT 0
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/* CON20 */
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#define CON20_REG_RST_MASK 0x01
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#define CON20_REG_RST_SHIFT 7
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#define CON20_PN_MASK 0x07
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#define CON20_PN_SHIFT 3
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#define CON20_REV_MASK 0x03
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#define CON20_REV_SHIFT 0
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/* REG12 status */
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enum BQ_FAULT {
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BQ_NORMAL_FAULT = 0,
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BQ_WATCHDOG_FAULT,
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BQ_OTG_FAULT,
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BQ_CHRG_NORMAL_FAULT,
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BQ_CHRG_INPUT_FAULT,
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BQ_CHRG_THERMAL_FAULT,
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BQ_CHRG_TIMER_EXPIRATION_FAULT,
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BQ_BAT_FAULT,
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BQ_NTC_FAULT,
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BQ_FAULT_MAX
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};
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/**********************************************************
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*
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* [Extern Function]
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*
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*********************************************************/
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/* CON0---------------------------------------------------- */
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extern void bq25890_set_en_hiz(u32 val);
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extern void bq25890_set_iinlim(u32 val);
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extern u32 bq25890_get_iinlim(void);
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/* CON1---------------------------------------------------- */
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/* CON2---------------------------------------------------- */
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extern void bq25890_set_force_dpdm(u32 val);
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extern void bq25890_set_auto_dpdm_en(u32 val);
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extern u32 bq25890_get_dpdm_status(void);
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/* CON3---------------------------------------------------- */
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extern void bq25890_set_wdt_rst(u32 val);
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extern void bq25890_set_otg_config(u32 val);
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extern void bq25890_set_chg_config(u32 val);
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extern void bq25890_set_sys_min(u32 val);
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/* CON4---------------------------------------------------- */
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extern void bq25890_set_ichg(u32 val);
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extern u32 bq25890_get_ichg(void);
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/* CON5---------------------------------------------------- */
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extern void bq25890_set_iprechg(u32 val);
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extern void bq25890_set_iterm(u32 val);
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/* CON6---------------------------------------------------- */
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extern void bq25890_set_vreg(u32 val);
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extern void bq25890_set_batlowv(u32 val);
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extern void bq25890_set_vrechg(u32 val);
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/* CON7---------------------------------------------------- */
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extern void bq25890_set_en_term(u32 val);
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extern void bq25890_set_watchdog(u32 val);
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extern void bq25890_set_en_timer(u32 val);
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extern void bq25890_set_chg_timer(u32 val);
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/* CON8---------------------------------------------------- */
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extern void bq25890_set_treg(u32 val);
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/* CON9---------------------------------------------------- */
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extern void bq25890_set_batfet_disable(u32 val);
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/* CON10---------------------------------------------------- */
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extern void bq25890_set_boost_lim(u32 val);
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/* CON11---------------------------------------------------- */
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extern u32 bq25890_get_system_status(void);
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extern u32 bq25890_get_vbus_stat(void);
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extern u32 bq25890_get_chrg_stat(void);
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extern u32 bq25890_get_pg_stat(void);
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extern u32 bq25890_get_vsys_stat(void);
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/* CON13---------------------------------------------------- */
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extern void bq25890_set_vindpm(u32 val);
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/* CON19---------------------------------------------------- */
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extern u32 bq25890_get_vdpm_stat(void);
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extern u32 bq25890_get_idpm_stat(void);
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extern u32 bq25890_get_current_iinlim(void);
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/* CON20---------------------------------------------------- */
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extern void bq25890_set_reg_rst(u32 val);
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extern u32 bq25890_get_pn(void);
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extern u32 bq25890_get_rev(void);
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/* --------------------------------------------------------- */
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extern void bq25890_dump_register(void);
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extern u32 bq25890_read_interface(u8 RegNum, u8 *val, u8 MASK, u8 SHIFT);
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s32 bq25890_control_interface(int cmd, void *data);
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extern int hw_charger_type_detection(void);
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/* spm utility */
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extern int slp_get_wake_reason(void);
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#endif /* _bq25890_SW_H_ */
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