519 lines
13 KiB
C
519 lines
13 KiB
C
/*
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* Copyright (C) 2003, Axis Communications AB.
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*/
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#include <asm/irq.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/profile.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/proc_fs.h>
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#include <linux/seq_file.h>
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#include <linux/kernel_stat.h>
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/intr_vect.h>
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#include <hwregs/intr_vect_defs.h>
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#define CPU_FIXED -1
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/* IRQ masks (refer to comment for crisv32_do_multiple) */
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#if TIMER0_INTR_VECT - FIRST_IRQ < 32
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#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
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#undef TIMER_VECT1
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#else
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#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
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#define TIMER_VECT1
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#endif
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#ifdef CONFIG_ETRAX_KGDB
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#if defined(CONFIG_ETRAX_KGDB_PORT0)
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#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT1)
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#define IGNOREMASK (1 << (SER1_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT2)
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#define IGNOREMASK (1 << (SER2_INTR_VECT - FIRST_IRQ))
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#elif defined(CONFIG_ETRAX_KGDB_PORT3)
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#define IGNOREMASK (1 << (SER3_INTR_VECT - FIRST_IRQ))
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#endif
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#endif
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DEFINE_SPINLOCK(irq_lock);
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struct cris_irq_allocation
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{
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int cpu; /* The CPU to which the IRQ is currently allocated. */
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cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
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};
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struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
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{ [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
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static unsigned long irq_regs[NR_CPUS] =
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{
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regi_irq,
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};
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#if NR_REAL_IRQS > 32
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#define NBR_REGS 2
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#else
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#define NBR_REGS 1
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#endif
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unsigned long cpu_irq_counters[NR_CPUS];
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unsigned long irq_counters[NR_REAL_IRQS];
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/* From irq.c. */
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extern void weird_irq(void);
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/* From entry.S. */
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extern void system_call(void);
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extern void nmi_interrupt(void);
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extern void multiple_interrupt(void);
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extern void gdb_handle_exception(void);
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extern void i_mmu_refill(void);
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extern void i_mmu_invalid(void);
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extern void i_mmu_access(void);
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extern void i_mmu_execute(void);
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extern void d_mmu_refill(void);
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extern void d_mmu_invalid(void);
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extern void d_mmu_access(void);
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extern void d_mmu_write(void);
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/* From kgdb.c. */
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extern void kgdb_init(void);
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extern void breakpoint(void);
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/* From traps.c. */
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extern void breakh_BUG(void);
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/*
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* Build the IRQ handler stubs using macros from irq.h.
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*/
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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BUILD_TIMER_IRQ(0x31, 0)
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#else
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BUILD_IRQ(0x31)
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#endif
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BUILD_IRQ(0x32)
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BUILD_IRQ(0x33)
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BUILD_IRQ(0x34)
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BUILD_IRQ(0x35)
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BUILD_IRQ(0x36)
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BUILD_IRQ(0x37)
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BUILD_IRQ(0x38)
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BUILD_IRQ(0x39)
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BUILD_IRQ(0x3a)
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BUILD_IRQ(0x3b)
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BUILD_IRQ(0x3c)
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BUILD_IRQ(0x3d)
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BUILD_IRQ(0x3e)
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BUILD_IRQ(0x3f)
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BUILD_IRQ(0x40)
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BUILD_IRQ(0x41)
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BUILD_IRQ(0x42)
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BUILD_IRQ(0x43)
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BUILD_IRQ(0x44)
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BUILD_IRQ(0x45)
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BUILD_IRQ(0x46)
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BUILD_IRQ(0x47)
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BUILD_IRQ(0x48)
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BUILD_IRQ(0x49)
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BUILD_IRQ(0x4a)
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#ifdef CONFIG_ETRAXFS
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BUILD_TIMER_IRQ(0x4b, 0)
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#else
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BUILD_IRQ(0x4b)
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#endif
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BUILD_IRQ(0x4c)
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BUILD_IRQ(0x4d)
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BUILD_IRQ(0x4e)
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BUILD_IRQ(0x4f)
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BUILD_IRQ(0x50)
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#if MACH_IRQS > 32
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BUILD_IRQ(0x51)
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BUILD_IRQ(0x52)
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BUILD_IRQ(0x53)
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BUILD_IRQ(0x54)
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BUILD_IRQ(0x55)
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BUILD_IRQ(0x56)
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BUILD_IRQ(0x57)
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BUILD_IRQ(0x58)
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BUILD_IRQ(0x59)
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BUILD_IRQ(0x5a)
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BUILD_IRQ(0x5b)
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BUILD_IRQ(0x5c)
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BUILD_IRQ(0x5d)
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BUILD_IRQ(0x5e)
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BUILD_IRQ(0x5f)
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BUILD_IRQ(0x60)
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BUILD_IRQ(0x61)
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BUILD_IRQ(0x62)
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BUILD_IRQ(0x63)
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BUILD_IRQ(0x64)
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BUILD_IRQ(0x65)
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BUILD_IRQ(0x66)
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BUILD_IRQ(0x67)
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BUILD_IRQ(0x68)
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BUILD_IRQ(0x69)
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BUILD_IRQ(0x6a)
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BUILD_IRQ(0x6b)
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BUILD_IRQ(0x6c)
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BUILD_IRQ(0x6d)
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BUILD_IRQ(0x6e)
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BUILD_IRQ(0x6f)
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BUILD_IRQ(0x70)
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#endif
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/* Pointers to the low-level handlers. */
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static void (*interrupt[MACH_IRQS])(void) = {
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IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
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IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
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IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
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IRQ0x3a_interrupt, IRQ0x3b_interrupt, IRQ0x3c_interrupt,
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IRQ0x3d_interrupt, IRQ0x3e_interrupt, IRQ0x3f_interrupt,
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IRQ0x40_interrupt, IRQ0x41_interrupt, IRQ0x42_interrupt,
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IRQ0x43_interrupt, IRQ0x44_interrupt, IRQ0x45_interrupt,
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IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
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IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
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IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
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IRQ0x4f_interrupt, IRQ0x50_interrupt,
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#if MACH_IRQS > 32
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IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
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IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
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IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
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IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
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IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
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IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
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IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
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IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
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IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
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IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
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IRQ0x6f_interrupt, IRQ0x70_interrupt,
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#endif
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};
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void
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block_irq(int irq, int cpu)
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{
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int intr_mask;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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/* Remember, 1 let thru, 0 block. */
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if (irq - FIRST_IRQ < 32) {
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 0);
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intr_mask &= ~(1 << (irq - FIRST_IRQ));
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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0, intr_mask);
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} else {
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 1);
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intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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1, intr_mask);
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}
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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void
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unblock_irq(int irq, int cpu)
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{
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int intr_mask;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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/* Remember, 1 let thru, 0 block. */
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if (irq - FIRST_IRQ < 32) {
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 0);
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intr_mask |= (1 << (irq - FIRST_IRQ));
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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0, intr_mask);
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} else {
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intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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rw_mask, 1);
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intr_mask |= (1 << (irq - FIRST_IRQ - 32));
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
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1, intr_mask);
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}
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spin_unlock_irqrestore(&irq_lock, flags);
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}
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/* Find out which CPU the irq should be allocated to. */
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static int irq_cpu(int irq)
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{
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int cpu;
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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cpu = irq_allocations[irq - FIRST_IRQ].cpu;
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/* Fixed interrupts stay on the local CPU. */
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if (cpu == CPU_FIXED)
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{
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spin_unlock_irqrestore(&irq_lock, flags);
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return smp_processor_id();
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}
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/* Let the interrupt stay if possible */
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if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
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goto out;
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/* IRQ must be moved to another CPU. */
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cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
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irq_allocations[irq - FIRST_IRQ].cpu = cpu;
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out:
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spin_unlock_irqrestore(&irq_lock, flags);
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return cpu;
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}
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void crisv32_mask_irq(int irq)
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{
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int cpu;
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for (cpu = 0; cpu < NR_CPUS; cpu++)
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block_irq(irq, cpu);
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}
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void crisv32_unmask_irq(int irq)
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{
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unblock_irq(irq, irq_cpu(irq));
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}
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static void enable_crisv32_irq(struct irq_data *data)
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{
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crisv32_unmask_irq(data->irq);
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}
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static void disable_crisv32_irq(struct irq_data *data)
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{
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crisv32_mask_irq(data->irq);
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}
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static int set_affinity_crisv32_irq(struct irq_data *data,
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const struct cpumask *dest, bool force)
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{
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unsigned long flags;
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spin_lock_irqsave(&irq_lock, flags);
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irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
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spin_unlock_irqrestore(&irq_lock, flags);
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return 0;
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}
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static struct irq_chip crisv32_irq_type = {
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.name = "CRISv32",
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.irq_shutdown = disable_crisv32_irq,
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.irq_enable = enable_crisv32_irq,
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.irq_disable = disable_crisv32_irq,
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.irq_set_affinity = set_affinity_crisv32_irq,
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};
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void
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set_exception_vector(int n, irqvectptr addr)
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{
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etrax_irv->v[n] = (irqvectptr) addr;
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}
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extern void do_IRQ(int irq, struct pt_regs * regs);
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void
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crisv32_do_IRQ(int irq, int block, struct pt_regs* regs)
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{
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/* Interrupts that may not be moved to another CPU may
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* skip blocking. This is currently only valid for the
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* timer IRQ and the IPI and is used for the timer
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* interrupt to avoid watchdog starvation.
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*/
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if (!block) {
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do_IRQ(irq, regs);
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return;
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}
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block_irq(irq, smp_processor_id());
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do_IRQ(irq, regs);
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unblock_irq(irq, irq_cpu(irq));
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}
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/* If multiple interrupts occur simultaneously we get a multiple
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* interrupt from the CPU and software has to sort out which
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* interrupts that happened. There are two special cases here:
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*
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* 1. Timer interrupts may never be blocked because of the
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* watchdog (refer to comment in include/asr/arch/irq.h)
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* 2. GDB serial port IRQs are unhandled here and will be handled
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* as a single IRQ when it strikes again because the GDB
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* stubb wants to save the registers in its own fashion.
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*/
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void
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crisv32_do_multiple(struct pt_regs* regs)
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{
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int cpu;
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int mask;
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int masked[NBR_REGS];
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int bit;
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int i;
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cpu = smp_processor_id();
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/* An extra irq_enter here to prevent softIRQs to run after
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* each do_IRQ. This will decrease the interrupt latency.
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*/
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irq_enter();
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for (i = 0; i < NBR_REGS; i++) {
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/* Get which IRQs that happened. */
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masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
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r_masked_vect, i);
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/* Calculate new IRQ mask with these IRQs disabled. */
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mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
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mask &= ~masked[i];
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/* Timer IRQ is never masked */
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#ifdef TIMER_VECT1
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if ((i == 1) && (masked[0] & TIMER_MASK))
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mask |= TIMER_MASK;
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#else
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if ((i == 0) && (masked[0] & TIMER_MASK))
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mask |= TIMER_MASK;
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#endif
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/* Block all the IRQs */
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
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/* Check for timer IRQ and handle it special. */
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#ifdef TIMER_VECT1
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if ((i == 1) && (masked[i] & TIMER_MASK)) {
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masked[i] &= ~TIMER_MASK;
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do_IRQ(TIMER0_INTR_VECT, regs);
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}
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#else
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if ((i == 0) && (masked[i] & TIMER_MASK)) {
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masked[i] &= ~TIMER_MASK;
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do_IRQ(TIMER0_INTR_VECT, regs);
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}
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#endif
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}
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#ifdef IGNORE_MASK
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/* Remove IRQs that can't be handled as multiple. */
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masked[0] &= ~IGNORE_MASK;
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#endif
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/* Handle the rest of the IRQs. */
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for (i = 0; i < NBR_REGS; i++) {
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for (bit = 0; bit < 32; bit++) {
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if (masked[i] & (1 << bit))
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do_IRQ(bit + FIRST_IRQ + i*32, regs);
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}
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}
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/* Unblock all the IRQs. */
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for (i = 0; i < NBR_REGS; i++) {
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mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
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mask |= masked[i];
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REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
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}
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/* This irq_exit() will trigger the soft IRQs. */
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irq_exit();
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}
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static int crisv32_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw_irq_num)
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{
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irq_set_chip_and_handler(virq, &crisv32_irq_type, handle_simple_irq);
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return 0;
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}
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static struct irq_domain_ops crisv32_irq_ops = {
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.map = crisv32_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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/*
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* This is called by start_kernel. It fixes the IRQ masks and setup the
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* interrupt vector table to point to bad_interrupt pointers.
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*/
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void __init
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init_IRQ(void)
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{
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int i;
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int j;
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reg_intr_vect_rw_mask vect_mask = {0};
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struct device_node *np;
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struct irq_domain *domain;
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/* Clear all interrupts masks. */
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for (i = 0; i < NBR_REGS; i++)
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REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
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for (i = 0; i < 256; i++)
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etrax_irv->v[i] = weird_irq;
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np = of_find_compatible_node(NULL, NULL, "axis,crisv32-intc");
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domain = irq_domain_add_legacy(np, NBR_INTR_VECT - FIRST_IRQ,
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FIRST_IRQ, FIRST_IRQ,
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&crisv32_irq_ops, NULL);
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BUG_ON(!domain);
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irq_set_default_host(domain);
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of_node_put(np);
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for (i = FIRST_IRQ, j = 0; j < NBR_INTR_VECT && j < MACH_IRQS; i++, j++)
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set_exception_vector(i, interrupt[j]);
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/* Mark Timer and IPI IRQs as CPU local */
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irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
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irq_set_status_flags(TIMER0_INTR_VECT, IRQ_PER_CPU);
|
|
irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
|
|
irq_set_status_flags(IPI_INTR_VECT, IRQ_PER_CPU);
|
|
|
|
set_exception_vector(0x00, nmi_interrupt);
|
|
set_exception_vector(0x30, multiple_interrupt);
|
|
|
|
/* Set up handler for various MMU bus faults. */
|
|
set_exception_vector(0x04, i_mmu_refill);
|
|
set_exception_vector(0x05, i_mmu_invalid);
|
|
set_exception_vector(0x06, i_mmu_access);
|
|
set_exception_vector(0x07, i_mmu_execute);
|
|
set_exception_vector(0x08, d_mmu_refill);
|
|
set_exception_vector(0x09, d_mmu_invalid);
|
|
set_exception_vector(0x0a, d_mmu_access);
|
|
set_exception_vector(0x0b, d_mmu_write);
|
|
|
|
#ifdef CONFIG_BUG
|
|
/* Break 14 handler, used to implement cheap BUG(). */
|
|
set_exception_vector(0x1e, breakh_BUG);
|
|
#endif
|
|
|
|
/* The system-call trap is reached by "break 13". */
|
|
set_exception_vector(0x1d, system_call);
|
|
|
|
/* Exception handlers for debugging, both user-mode and kernel-mode. */
|
|
|
|
/* Break 8. */
|
|
set_exception_vector(0x18, gdb_handle_exception);
|
|
/* Hardware single step. */
|
|
set_exception_vector(0x3, gdb_handle_exception);
|
|
/* Hardware breakpoint. */
|
|
set_exception_vector(0xc, gdb_handle_exception);
|
|
|
|
#ifdef CONFIG_ETRAX_KGDB
|
|
kgdb_init();
|
|
/* Everything is set up; now trap the kernel. */
|
|
breakpoint();
|
|
#endif
|
|
}
|
|
|