552 lines
16 KiB
C
552 lines
16 KiB
C
/*
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* Performance counter support for POWER6 processors.
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*
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/perf_event.h>
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#include <linux/string.h>
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#include <asm/reg.h>
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#include <asm/cputable.h>
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/*
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* Bits in event code for POWER6
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*/
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#define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
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#define PM_PMC_MSK 0x7
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#define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
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#define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */
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#define PM_UNIT_MSK 0xf
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#define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH)
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#define PM_LLAV 0x8000 /* Load lookahead match value */
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#define PM_LLA 0x4000 /* Load lookahead match enable */
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#define PM_BYTE_SH 12 /* Byte of event bus to use */
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#define PM_BYTE_MSK 3
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#define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */
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#define PM_SUBUNIT_MSK 7
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#define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
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#define PM_PMCSEL_MSK 0xff /* PMCxSEL value */
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#define PM_BUSEVENT_MSK 0xf3700
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/*
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* Bits in MMCR1 for POWER6
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*/
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#define MMCR1_TTM0SEL_SH 60
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#define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
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#define MMCR1_TTMSEL_MSK 0xf
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#define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
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#define MMCR1_NESTSEL_SH 45
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#define MMCR1_NESTSEL_MSK 0x7
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#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
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#define MMCR1_PMC1_LLA (1ul << 44)
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#define MMCR1_PMC1_LLA_VALUE (1ul << 39)
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#define MMCR1_PMC1_ADDR_SEL (1ul << 35)
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#define MMCR1_PMC1SEL_SH 24
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#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
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#define MMCR1_PMCSEL_MSK 0xff
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/*
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* Map of which direct events on which PMCs are marked instruction events.
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* Indexed by PMCSEL value >> 1.
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* Bottom 4 bits are a map of which PMCs are interesting,
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* top 4 bits say what sort of event:
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* 0 = direct marked event,
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* 1 = byte decode event,
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* 4 = add/and event (PMC1 -> bits 0 & 4),
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* 5 = add/and event (PMC1 -> bits 1 & 5),
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* 6 = add/and event (PMC1 -> bits 2 & 6),
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* 7 = add/and event (PMC1 -> bits 3 & 7).
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*/
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static unsigned char direct_event_is_marked[0x60 >> 1] = {
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0, /* 00 */
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0, /* 02 */
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0, /* 04 */
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0x07, /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
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0x04, /* 08 PM_MRK_DFU_FIN */
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0x06, /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
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0, /* 0c */
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0, /* 0e */
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0x02, /* 10 PM_MRK_INST_DISP */
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0x08, /* 12 PM_MRK_LSU_DERAT_MISS */
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0, /* 14 */
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0, /* 16 */
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0x0c, /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
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0x0f, /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
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0x01, /* 1c PM_MRK_INST_ISSUED */
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0, /* 1e */
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0, /* 20 */
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0, /* 22 */
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0, /* 24 */
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0, /* 26 */
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0x15, /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
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0, /* 2a */
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0, /* 2c */
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0, /* 2e */
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0x4f, /* 30 */
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0x7f, /* 32 */
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0x4f, /* 34 */
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0x5f, /* 36 */
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0x6f, /* 38 */
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0x4f, /* 3a */
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0, /* 3c */
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0x08, /* 3e PM_MRK_INST_TIMEO */
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0x1f, /* 40 */
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0x1f, /* 42 */
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0x1f, /* 44 */
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0x1f, /* 46 */
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0x1f, /* 48 */
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0x1f, /* 4a */
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0x1f, /* 4c */
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0x1f, /* 4e */
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0, /* 50 */
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0x05, /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
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0x1c, /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
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0x02, /* 56 PM_MRK_LD_MISS_L1 */
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0, /* 58 */
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0, /* 5a */
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0, /* 5c */
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0, /* 5e */
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};
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/*
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* Masks showing for each unit which bits are marked events.
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* These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
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*/
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static u32 marked_bus_events[16] = {
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0x01000000, /* direct events set 1: byte 3 bit 0 */
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0x00010000, /* direct events set 2: byte 2 bit 0 */
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0, 0, 0, 0, /* IDU, IFU, nest: nothing */
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0x00000088, /* VMX set 1: byte 0 bits 3, 7 */
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0x000000c0, /* VMX set 2: byte 0 bits 4-7 */
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0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
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0xff010000u, /* LSU set 2: byte 2 bit 0, all of byte 3 */
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0, /* LSU set 3 */
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0x00000010, /* VMX set 3: byte 0 bit 4 */
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0, /* BFP set 1 */
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0x00000022, /* BFP set 2: byte 0 bits 1, 5 */
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0, 0
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};
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/*
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* Returns 1 if event counts things relating to marked instructions
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* and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
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*/
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static int power6_marked_instr_event(u64 event)
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{
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int pmc, psel, ptype;
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int bit, byte, unit;
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u32 mask;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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psel = (event & PM_PMCSEL_MSK) >> 1; /* drop edge/level bit */
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if (pmc >= 5)
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return 0;
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bit = -1;
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if (psel < sizeof(direct_event_is_marked)) {
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ptype = direct_event_is_marked[psel];
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if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
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return 0;
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ptype >>= 4;
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if (ptype == 0)
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return 1;
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if (ptype == 1)
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bit = 0;
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else
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bit = ptype ^ (pmc - 1);
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} else if ((psel & 0x48) == 0x40)
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bit = psel & 7;
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if (!(event & PM_BUSEVENT_MSK) || bit == -1)
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return 0;
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
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mask = marked_bus_events[unit];
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return (mask >> (byte * 8 + bit)) & 1;
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}
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/*
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* Assign PMC numbers and compute MMCR1 value for a set of events
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*/
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static int p6_compute_mmcr(u64 event[], int n_ev,
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unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[])
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{
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unsigned long mmcr1 = 0;
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unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
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int i;
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unsigned int pmc, ev, b, u, s, psel;
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unsigned int ttmset = 0;
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unsigned int pmc_inuse = 0;
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if (n_ev > 6)
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return -1;
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for (i = 0; i < n_ev; ++i) {
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pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc_inuse & (1 << (pmc - 1)))
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return -1; /* collision! */
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pmc_inuse |= 1 << (pmc - 1);
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}
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}
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for (i = 0; i < n_ev; ++i) {
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ev = event[i];
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pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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--pmc;
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} else {
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/* can go on any PMC; find a free one */
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for (pmc = 0; pmc < 4; ++pmc)
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if (!(pmc_inuse & (1 << pmc)))
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break;
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if (pmc >= 4)
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return -1;
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pmc_inuse |= 1 << pmc;
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}
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hwc[i] = pmc;
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psel = ev & PM_PMCSEL_MSK;
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if (ev & PM_BUSEVENT_MSK) {
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/* this event uses the event bus */
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b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
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u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
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/* check for conflict on this byte of event bus */
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if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
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return -1;
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mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
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ttmset |= 1 << b;
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if (u == 5) {
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/* Nest events have a further mux */
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s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
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if ((ttmset & 0x10) &&
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MMCR1_NESTSEL(mmcr1) != s)
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return -1;
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ttmset |= 0x10;
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mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
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}
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if (0x30 <= psel && psel <= 0x3d) {
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/* these need the PMCx_ADDR_SEL bits */
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if (b >= 2)
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mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
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}
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/* bus select values are different for PMC3/4 */
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if (pmc >= 2 && (psel & 0x90) == 0x80)
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psel ^= 0x20;
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}
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if (ev & PM_LLA) {
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mmcr1 |= MMCR1_PMC1_LLA >> pmc;
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if (ev & PM_LLAV)
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mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
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}
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if (power6_marked_instr_event(event[i]))
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mmcra |= MMCRA_SAMPLE_ENABLE;
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if (pmc < 4)
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mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
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}
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mmcr[0] = 0;
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if (pmc_inuse & 1)
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mmcr[0] = MMCR0_PMC1CE;
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if (pmc_inuse & 0xe)
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mmcr[0] |= MMCR0_PMCjCE;
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mmcr[1] = mmcr1;
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mmcr[2] = mmcra;
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return 0;
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}
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/*
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* Layout of constraint bits:
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*
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* 0-1 add field: number of uses of PMC1 (max 1)
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* 2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
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* 12-15 add field: number of uses of PMC1-4 (max 4)
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* 16-19 select field: unit on byte 0 of event bus
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* 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
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* 32-34 select field: nest (subunit) event selector
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*/
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static int p6_get_constraint(u64 event, unsigned long *maskp,
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unsigned long *valp)
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{
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int pmc, byte, sh, subunit;
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unsigned long mask = 0, value = 0;
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc) {
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if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
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return -1;
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sh = (pmc - 1) * 2;
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mask |= 2 << sh;
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value |= 1 << sh;
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}
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if (event & PM_BUSEVENT_MSK) {
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byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
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sh = byte * 4 + (16 - PM_UNIT_SH);
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mask |= PM_UNIT_MSKS << sh;
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value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
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if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
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subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
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mask |= (unsigned long)PM_SUBUNIT_MSK << 32;
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value |= (unsigned long)subunit << 32;
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}
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}
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if (pmc <= 4) {
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mask |= 0x8000; /* add field for count of PMC1-4 uses */
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value |= 0x1000;
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}
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*maskp = mask;
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*valp = value;
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return 0;
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}
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static int p6_limited_pmc_event(u64 event)
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{
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int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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return pmc == 5 || pmc == 6;
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}
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#define MAX_ALT 4 /* at most 4 alternatives for any event */
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static const unsigned int event_alternatives[][MAX_ALT] = {
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{ 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */
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{ 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
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{ 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */
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{ 0x10000a, 0x2000f4, 0x600005 }, /* PM_RUN_CYC */
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{ 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */
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{ 0x10000e, 0x400010 }, /* PM_PURR */
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{ 0x100010, 0x4000f8 }, /* PM_FLUSH */
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{ 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */
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{ 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */
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{ 0x100054, 0x2000f0 }, /* PM_ST_FIN */
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{ 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */
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{ 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */
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{ 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */
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{ 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */
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{ 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */
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{ 0x200012, 0x300012 }, /* PM_INST_DISP */
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{ 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */
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{ 0x2000f8, 0x300010 }, /* PM_EXT_INT */
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{ 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */
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{ 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */
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{ 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */
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{ 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */
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{ 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */
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};
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/*
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* This could be made more efficient with a binary search on
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* a presorted list, if necessary
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*/
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static int find_alternatives_list(u64 event)
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{
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int i, j;
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unsigned int alt;
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for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
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if (event < event_alternatives[i][0])
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return -1;
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for (j = 0; j < MAX_ALT; ++j) {
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alt = event_alternatives[i][j];
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if (!alt || event < alt)
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break;
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if (event == alt)
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return i;
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}
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}
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return -1;
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}
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static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int i, j, nlim;
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unsigned int psel, pmc;
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unsigned int nalt = 1;
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u64 aevent;
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alt[0] = event;
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nlim = p6_limited_pmc_event(event);
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/* check the alternatives table */
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i = find_alternatives_list(event);
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if (i >= 0) {
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/* copy out alternatives from list */
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for (j = 0; j < MAX_ALT; ++j) {
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aevent = event_alternatives[i][j];
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if (!aevent)
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break;
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if (aevent != event)
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alt[nalt++] = aevent;
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nlim += p6_limited_pmc_event(aevent);
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}
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} else {
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/* Check for alternative ways of computing sum events */
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/* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
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psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */
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pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
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if (pmc && (psel == 0x32 || psel == 0x34))
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alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
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((5 - pmc) << PM_PMC_SH);
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/* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
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if (pmc && (psel == 0x38 || psel == 0x3a))
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alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
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((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
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}
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if (flags & PPMU_ONLY_COUNT_RUN) {
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/*
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* We're only counting in RUN state,
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* so PM_CYC is equivalent to PM_RUN_CYC,
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* PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
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* This doesn't include alternatives that don't provide
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* any extra flexibility in assigning PMCs (e.g.
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* 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
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* Note that even with these additional alternatives
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* we never end up with more than 4 alternatives for any event.
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*/
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j = nalt;
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for (i = 0; i < nalt; ++i) {
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switch (alt[i]) {
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case 0x1e: /* PM_CYC */
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alt[j++] = 0x600005; /* PM_RUN_CYC */
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++nlim;
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break;
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case 0x10000a: /* PM_RUN_CYC */
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alt[j++] = 0x1e; /* PM_CYC */
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break;
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case 2: /* PM_INST_CMPL */
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alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */
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++nlim;
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break;
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case 0x500009: /* PM_RUN_INST_CMPL */
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alt[j++] = 2; /* PM_INST_CMPL */
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break;
|
|
case 0x10000e: /* PM_PURR */
|
|
alt[j++] = 0x4000f4; /* PM_RUN_PURR */
|
|
break;
|
|
case 0x4000f4: /* PM_RUN_PURR */
|
|
alt[j++] = 0x10000e; /* PM_PURR */
|
|
break;
|
|
}
|
|
}
|
|
nalt = j;
|
|
}
|
|
|
|
if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
|
|
/* remove the limited PMC events */
|
|
j = 0;
|
|
for (i = 0; i < nalt; ++i) {
|
|
if (!p6_limited_pmc_event(alt[i])) {
|
|
alt[j] = alt[i];
|
|
++j;
|
|
}
|
|
}
|
|
nalt = j;
|
|
} else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
|
|
/* remove all but the limited PMC events */
|
|
j = 0;
|
|
for (i = 0; i < nalt; ++i) {
|
|
if (p6_limited_pmc_event(alt[i])) {
|
|
alt[j] = alt[i];
|
|
++j;
|
|
}
|
|
}
|
|
nalt = j;
|
|
}
|
|
|
|
return nalt;
|
|
}
|
|
|
|
static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
|
|
{
|
|
/* Set PMCxSEL to 0 to disable PMCx */
|
|
if (pmc <= 3)
|
|
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
|
|
}
|
|
|
|
static int power6_generic_events[] = {
|
|
[PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = 2,
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */
|
|
[PERF_COUNT_HW_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
|
|
};
|
|
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
|
|
|
/*
|
|
* Table of generalized cache-related events.
|
|
* 0 means not supported, -1 means nonsensical, other values
|
|
* are event codes.
|
|
* The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
|
|
*/
|
|
static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
|
[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { 0x280030, 0x80080 },
|
|
[C(OP_WRITE)] = { 0x180032, 0x80088 },
|
|
[C(OP_PREFETCH)] = { 0x810a4, 0 },
|
|
},
|
|
[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { 0, 0x100056 },
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
[C(OP_PREFETCH)] = { 0x4008c, 0 },
|
|
},
|
|
[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { 0x150730, 0x250532 },
|
|
[C(OP_WRITE)] = { 0x250432, 0x150432 },
|
|
[C(OP_PREFETCH)] = { 0x810a6, 0 },
|
|
},
|
|
[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { 0, 0x20000e },
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
},
|
|
[C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { 0, 0x420ce },
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
},
|
|
[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { 0x430e6, 0x400052 },
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
},
|
|
[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
|
|
[C(OP_READ)] = { -1, -1 },
|
|
[C(OP_WRITE)] = { -1, -1 },
|
|
[C(OP_PREFETCH)] = { -1, -1 },
|
|
},
|
|
};
|
|
|
|
static struct power_pmu power6_pmu = {
|
|
.name = "POWER6",
|
|
.n_counter = 6,
|
|
.max_alternatives = MAX_ALT,
|
|
.add_fields = 0x1555,
|
|
.test_adder = 0x3000,
|
|
.compute_mmcr = p6_compute_mmcr,
|
|
.get_constraint = p6_get_constraint,
|
|
.get_alternatives = p6_get_alternatives,
|
|
.disable_pmc = p6_disable_pmc,
|
|
.limited_pmc_event = p6_limited_pmc_event,
|
|
.flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
|
|
.n_generic = ARRAY_SIZE(power6_generic_events),
|
|
.generic_events = power6_generic_events,
|
|
.cache_events = &power6_cache_events,
|
|
};
|
|
|
|
static int __init init_power6_pmu(void)
|
|
{
|
|
if (!cur_cpu_spec->oprofile_cpu_type ||
|
|
strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
|
|
return -ENODEV;
|
|
|
|
return register_power_pmu(&power6_pmu);
|
|
}
|
|
|
|
early_initcall(init_power6_pmu);
|