385 lines
10 KiB
C
385 lines
10 KiB
C
/*======================================================================
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Device driver for the PCMCIA control functionality of PXA2xx
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microprocessors.
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The contents of this file may be used under the
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terms of the GNU Public License version 2 (the "GPL")
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(c) Ian Molton (spyro@f2s.com) 2003
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(c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
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derived from sa11xx_base.c
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Portions created by John G. Dorsey are
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Copyright (C) 1999 John G. Dorsey.
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======================================================================*/
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <mach/hardware.h>
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#include <mach/smemc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <mach/pxa2xx-regs.h>
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#include <asm/mach-types.h>
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#include <pcmcia/ss.h>
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#include <pcmcia/cistpl.h>
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#include "soc_common.h"
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#include "pxa2xx_base.h"
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/*
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* Personal Computer Memory Card International Association (PCMCIA) sockets
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*/
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#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
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#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
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#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
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#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
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#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
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#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
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#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
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#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
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#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
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#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
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#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
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#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
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#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
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#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
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(0x20000000 + (Nb) * PCMCIASp)
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#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
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#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
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(_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
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#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
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(_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
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#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
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#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
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#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
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#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
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#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
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#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
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#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
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#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
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#define MCXX_SETUP_MASK (0x7f)
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#define MCXX_ASST_MASK (0x1f)
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#define MCXX_HOLD_MASK (0x3f)
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#define MCXX_SETUP_SHIFT (0)
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#define MCXX_ASST_SHIFT (7)
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#define MCXX_HOLD_SHIFT (14)
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static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
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u_int mem_clk_10khz)
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{
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u_int code = pcmcia_cycle_ns * mem_clk_10khz;
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return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
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}
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static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
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u_int mem_clk_10khz)
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{
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u_int code = pcmcia_cycle_ns * mem_clk_10khz;
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return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
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}
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static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
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u_int mem_clk_10khz)
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{
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u_int code = pcmcia_cycle_ns * mem_clk_10khz;
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return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
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}
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/* This function returns the (approximate) command assertion period, in
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* nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
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*/
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static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
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u_int pcmcia_mcxx_asst)
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{
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return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
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}
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static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
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{
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uint32_t val;
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val = ((pxa2xx_mcxx_setup(speed, clock)
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& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
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| ((pxa2xx_mcxx_asst(speed, clock)
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& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
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| ((pxa2xx_mcxx_hold(speed, clock)
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& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
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__raw_writel(val, MCMEM(sock));
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return 0;
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}
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static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
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{
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uint32_t val;
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val = ((pxa2xx_mcxx_setup(speed, clock)
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& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
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| ((pxa2xx_mcxx_asst(speed, clock)
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& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
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| ((pxa2xx_mcxx_hold(speed, clock)
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& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
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__raw_writel(val, MCIO(sock));
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return 0;
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}
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static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
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{
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uint32_t val;
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val = ((pxa2xx_mcxx_setup(speed, clock)
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& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
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| ((pxa2xx_mcxx_asst(speed, clock)
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& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
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| ((pxa2xx_mcxx_hold(speed, clock)
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& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
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__raw_writel(val, MCATT(sock));
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return 0;
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}
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static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
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{
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struct soc_pcmcia_timing timing;
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int sock = skt->nr;
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soc_common_pcmcia_get_timing(skt, &timing);
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pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
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pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
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pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
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return 0;
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}
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static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
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{
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unsigned long clk = clk_get_rate(skt->clk);
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return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
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}
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#ifdef CONFIG_CPU_FREQ
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static int
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pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
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unsigned long val,
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struct cpufreq_freqs *freqs)
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{
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switch (val) {
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case CPUFREQ_PRECHANGE:
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if (freqs->new > freqs->old) {
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debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
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"pre-updating\n",
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freqs->new / 1000, (freqs->new / 100) % 10,
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freqs->old / 1000, (freqs->old / 100) % 10);
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pxa2xx_pcmcia_set_timing(skt);
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}
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break;
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case CPUFREQ_POSTCHANGE:
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if (freqs->new < freqs->old) {
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debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
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"post-updating\n",
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freqs->new / 1000, (freqs->new / 100) % 10,
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freqs->old / 1000, (freqs->old / 100) % 10);
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pxa2xx_pcmcia_set_timing(skt);
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}
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break;
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}
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return 0;
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}
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#endif
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void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
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{
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/*
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* We have at least one socket, so set MECR:CIT
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* (Card Is There)
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*/
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uint32_t mecr = MECR_CIT;
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/* Set MECR:NOS (Number Of Sockets) */
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if ((ops->first + ops->nr) > 1 ||
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machine_is_viper() || machine_is_arcom_zeus())
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mecr |= MECR_NOS;
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__raw_writel(mecr, MECR);
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}
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EXPORT_SYMBOL(pxa2xx_configure_sockets);
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static const char *skt_names[] = {
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"PCMCIA socket 0",
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"PCMCIA socket 1",
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};
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#define SKT_DEV_INFO_SIZE(n) \
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(sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
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int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
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{
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skt->res_skt.start = _PCMCIA(skt->nr);
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skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
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skt->res_skt.name = skt_names[skt->nr];
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skt->res_skt.flags = IORESOURCE_MEM;
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skt->res_io.start = _PCMCIAIO(skt->nr);
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skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
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skt->res_io.name = "io";
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skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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skt->res_mem.start = _PCMCIAMem(skt->nr);
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skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
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skt->res_mem.name = "memory";
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skt->res_mem.flags = IORESOURCE_MEM;
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skt->res_attr.start = _PCMCIAAttr(skt->nr);
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skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
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skt->res_attr.name = "attribute";
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skt->res_attr.flags = IORESOURCE_MEM;
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return soc_pcmcia_add_one(skt);
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}
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EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
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void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
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{
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/* Provide our PXA2xx specific timing routines. */
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ops->set_timing = pxa2xx_pcmcia_set_timing;
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#ifdef CONFIG_CPU_FREQ
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ops->frequency_change = pxa2xx_pcmcia_frequency_change;
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#endif
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}
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EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
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static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
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{
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int i, ret = 0;
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struct pcmcia_low_level *ops;
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struct skt_dev_info *sinfo;
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struct soc_pcmcia_socket *skt;
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struct clk *clk;
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ops = (struct pcmcia_low_level *)dev->dev.platform_data;
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if (!ops) {
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ret = -ENODEV;
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goto err0;
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}
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if (cpu_is_pxa320() && ops->nr > 1) {
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dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
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ret = -EINVAL;
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goto err0;
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}
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clk = devm_clk_get(&dev->dev, NULL);
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if (IS_ERR(clk))
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return -ENODEV;
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pxa2xx_drv_pcmcia_ops(ops);
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sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
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GFP_KERNEL);
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if (!sinfo)
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return -ENOMEM;
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sinfo->nskt = ops->nr;
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/* Initialize processor specific parameters */
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for (i = 0; i < ops->nr; i++) {
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skt = &sinfo->skt[i];
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skt->nr = ops->first + i;
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skt->clk = clk;
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soc_pcmcia_init_one(skt, ops, &dev->dev);
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ret = pxa2xx_drv_pcmcia_add_one(skt);
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if (ret)
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goto err1;
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}
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pxa2xx_configure_sockets(&dev->dev, ops);
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dev_set_drvdata(&dev->dev, sinfo);
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return 0;
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err1:
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while (--i >= 0)
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soc_pcmcia_remove_one(&sinfo->skt[i]);
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err0:
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return ret;
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}
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static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
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{
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struct skt_dev_info *sinfo = platform_get_drvdata(dev);
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int i;
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for (i = 0; i < sinfo->nskt; i++)
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soc_pcmcia_remove_one(&sinfo->skt[i]);
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return 0;
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}
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static int pxa2xx_drv_pcmcia_resume(struct device *dev)
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{
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struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
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pxa2xx_configure_sockets(dev, ops);
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return 0;
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}
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static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
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.resume = pxa2xx_drv_pcmcia_resume,
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};
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static struct platform_driver pxa2xx_pcmcia_driver = {
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.probe = pxa2xx_drv_pcmcia_probe,
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.remove = pxa2xx_drv_pcmcia_remove,
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.driver = {
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.name = "pxa2xx-pcmcia",
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.pm = &pxa2xx_drv_pcmcia_pm_ops,
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},
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};
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static int __init pxa2xx_pcmcia_init(void)
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{
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return platform_driver_register(&pxa2xx_pcmcia_driver);
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}
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static void __exit pxa2xx_pcmcia_exit(void)
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{
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platform_driver_unregister(&pxa2xx_pcmcia_driver);
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}
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fs_initcall(pxa2xx_pcmcia_init);
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module_exit(pxa2xx_pcmcia_exit);
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MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
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MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-pcmcia");
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