huawei-mrd-kernel/Documentation/devicetree/bindings/interrupt-controller/img,meta-intc.txt

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* Meta External Trigger Controller Binding
This binding specifies what properties must be available in the device tree
representation of a Meta external trigger controller.
Required properties:
- compatible: Specifies the compatibility list for the interrupt controller.
The type shall be <string> and the value shall include "img,meta-intc".
- num-banks: Specifies the number of interrupt banks (each of which can
handle 32 interrupt sources).
- interrupt-controller: The presence of this property identifies the node
as an interrupt controller. No property value shall be defined.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 2.
- #address-cells: Specifies the number of cells needed to encode an
address. The type shall be <u32> and the value shall be 0. As such,
'interrupt-map' nodes do not have to specify a parent unit address.
Optional properties:
- no-mask: The controller doesn't have any mask registers.
* Interrupt Specifier Definition
Interrupt specifiers consists of 2 cells encoded as follows:
- <1st-cell>: The interrupt-number that identifies the interrupt source.
- <2nd-cell>: The Linux interrupt flags containing level-sense information,
encoded as follows:
1 = edge triggered
4 = level-sensitive
* Examples
Example 1:
/*
* Meta external trigger block
*/
intc: intc {
// This is an interrupt controller node.
interrupt-controller;
// No address cells so that 'interrupt-map' nodes which
// reference this interrupt controller node do not need a parent
// address specifier.
#address-cells = <0>;
// Two cells to encode interrupt sources.
#interrupt-cells = <2>;
// Number of interrupt banks
num-banks = <2>;
// No HWMASKEXT is available (specify on Chorus2 and Comet ES1)
no-mask;
// Compatible with Meta hardware trigger block.
compatible = "img,meta-intc";
};
Example 2:
/*
* An interrupt generating device that is wired to a Meta external
* trigger block.
*/
uart1: uart@0x02004c00 {
// Interrupt source '5' that is level-sensitive.
// Note that there are only two cells as specified in the
// interrupt parent's '#interrupt-cells' property.
interrupts = <5 4 /* level */>;
// The interrupt controller that this device is wired to.
interrupt-parent = <&intc>;
};