160 lines
4 KiB
C
160 lines
4 KiB
C
/*
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* local apic based NMI watchdog for various CPUs.
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*
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* This file also handles reservation of performance counters for coordination
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* with other users (like oprofile).
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*
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* Note that these events normally don't tick when the CPU idles. This means
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* the frequency varies with CPU load.
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*
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* Original code for K7/P6 written by Keith Owens
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*
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*/
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#include <linux/percpu.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/smp.h>
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#include <asm/nmi.h>
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#include <linux/kprobes.h>
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#include <asm/apic.h>
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#include <asm/perf_event.h>
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/*
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* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
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* offset from MSR_P4_BSU_ESCR0.
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*
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* It will be the max for all platforms (for now)
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*/
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#define NMI_MAX_COUNTER_BITS 66
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/*
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* perfctr_nmi_owner tracks the ownership of the perfctr registers:
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* evtsel_nmi_owner tracks the ownership of the event selection
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* - different performance counters/ event selection may be reserved for
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* different subsystems this reservation system just tries to coordinate
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* things a little
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*/
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static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
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static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
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/* converts an msr to an appropriate reservation bit */
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static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
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{
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/* returns the bit offset of the performance counter register */
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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if (msr >= MSR_F15H_PERF_CTR)
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return (msr - MSR_F15H_PERF_CTR) >> 1;
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return msr - MSR_K7_PERFCTR0;
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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return msr - MSR_ARCH_PERFMON_PERFCTR0;
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switch (boot_cpu_data.x86) {
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case 6:
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return msr - MSR_P6_PERFCTR0;
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case 11:
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return msr - MSR_KNC_PERFCTR0;
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case 15:
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return msr - MSR_P4_BPU_PERFCTR0;
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}
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}
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return 0;
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}
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/*
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* converts an msr to an appropriate reservation bit
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* returns the bit offset of the event selection register
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*/
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static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
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{
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/* returns the bit offset of the event selection register */
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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if (msr >= MSR_F15H_PERF_CTL)
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return (msr - MSR_F15H_PERF_CTL) >> 1;
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return msr - MSR_K7_EVNTSEL0;
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case X86_VENDOR_INTEL:
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if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
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return msr - MSR_ARCH_PERFMON_EVENTSEL0;
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switch (boot_cpu_data.x86) {
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case 6:
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return msr - MSR_P6_EVNTSEL0;
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case 11:
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return msr - MSR_KNC_EVNTSEL0;
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case 15:
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return msr - MSR_P4_BSU_ESCR0;
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}
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}
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return 0;
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}
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/* checks for a bit availability (hack for oprofile) */
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int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
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{
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BUG_ON(counter > NMI_MAX_COUNTER_BITS);
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return !test_bit(counter, perfctr_nmi_owner);
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}
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EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
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int reserve_perfctr_nmi(unsigned int msr)
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{
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unsigned int counter;
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counter = nmi_perfctr_msr_to_bit(msr);
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/* register not managed by the allocator? */
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if (counter > NMI_MAX_COUNTER_BITS)
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return 1;
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if (!test_and_set_bit(counter, perfctr_nmi_owner))
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return 1;
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return 0;
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}
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EXPORT_SYMBOL(reserve_perfctr_nmi);
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void release_perfctr_nmi(unsigned int msr)
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{
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unsigned int counter;
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counter = nmi_perfctr_msr_to_bit(msr);
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/* register not managed by the allocator? */
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if (counter > NMI_MAX_COUNTER_BITS)
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return;
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clear_bit(counter, perfctr_nmi_owner);
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}
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EXPORT_SYMBOL(release_perfctr_nmi);
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int reserve_evntsel_nmi(unsigned int msr)
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{
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unsigned int counter;
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counter = nmi_evntsel_msr_to_bit(msr);
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/* register not managed by the allocator? */
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if (counter > NMI_MAX_COUNTER_BITS)
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return 1;
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if (!test_and_set_bit(counter, evntsel_nmi_owner))
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return 1;
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return 0;
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}
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EXPORT_SYMBOL(reserve_evntsel_nmi);
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void release_evntsel_nmi(unsigned int msr)
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{
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unsigned int counter;
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counter = nmi_evntsel_msr_to_bit(msr);
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/* register not managed by the allocator? */
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if (counter > NMI_MAX_COUNTER_BITS)
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return;
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clear_bit(counter, evntsel_nmi_owner);
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}
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EXPORT_SYMBOL(release_evntsel_nmi);
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